1. Field of the Invention
The present invention generally relates to interconnections within layers of a semiconductor wafer. More particularly, the present invention relates to interconnections in low-K dielectric materials and ultra low-K dielectric materials.
2. Description of the Related Art
In general, semiconductor devices are manufactured or fabricated on disks of semiconducting materials called wafers or slices. More particularly, wafers are initially sliced from a silicon ingot. The wafers then undergo multiple masking, etching, and deposition processes to form the electronic circuitry of semiconductor devices.
During the past decades, the semiconductor industry has increased the power of semiconductor devices in accordance with Moore's law, which predicts that the power of semiconductor devices will double every 18 months. This increase in the power of semiconductor devices has been achieved in part by decreasing the feature size (i.e., the smallest dimension present on a device) of these semiconductor devices. In fact, the feature size of semiconductor devices has quickly gone from 0.35 microns to 0.25 microns, and now to 0.18 microns. Undoubtedly, this trend toward smaller semiconductor devices is likely to proceed well beyond the sub-0.18 micron stage.
However, one potential limiting factor to developing more powerful semiconductor devices is the increasing signal delays at the interconnections (the lines of conductors, which connect elements of a single semiconductor device and/or connect any number of semiconductor devices together). As the feature size of semiconductor devices has decreased, the density of interconnections on the devices has increased. The closer proximity of interconnections, however, increases the line-to-line capacitance of the interconnections, which results in greater signal delay at the interconnections. In general, interconnection delays have been found to increase with the square of the reduction in feature size. In contrast, gate delays have been found to decrease linearly with the reduction in feature size. As such, there is generally a net increase in overall delays with a reduction in feature size.
One conventional approach to compensate for this increase in interconnection delay has been to add more layers of metal. However, this approach has the disadvantage of increasing production costs associated with forming the additional layers of metal. Furthermore, these additional layers of metal generate additional heat, which can be adverse to both chip performance and reliability.
An alternative approach to compensate for the increase in interconnection delay is to use dielectric materials having low dielectric constants (low-K dielectrics). However, because low-K dielectric materials have porous microstructures, they also have lower mechanical integrity and thermal conductivity than other dielectric materials. Consequently, low-K dielectric materials typically cannot sustain the stress and pressure applied to them during a conventional damascene process.
In a conventional damascene process, metal is patterned within canal-like trenches and/or via. The deposited metal is then typically polished back using chemical mechanical polishing (CMP). In general, depending on the interconnection structure design, anywhere from half a micron to 1.5 millimeters of metal can be polished.
However, when metal is patterned within trenches and/or via of a low-K dielectric material, and then polished back using CMP, the low-K dielectric material can fracture or pull away from the metal within the trenches and/or via due to the stress and pressure of CMP. Consequently, strong or rigid structures have been formed within the low-K dielectric materials to help them sustain the stress and pressure applied during CMP. However, building such structures within the low-K dielectric materials can be costly and can increase the interconnection delays within the device that the low-K dielectric materials were intended to reduce.